The present invention relates generally to electrical, electronic and computer arts, and more particularly relates to memory storage components and systems.
In a memory system employing six-transistor (6T) or eight-transistor (8T) static random access memory (SRAM) cells, in order to improve the stability of conventional 6T or 8T memory cells, a variety of techniques have been proposed. Such techniques include, for example, providing dual-voltage supplies, using multiple-threshold voltage (multi-VT) transistor devices, decreasing the length of bit lines used in the memory cells, employing power supply boosting via interconnects, adding transistors to the cells, and using a charge pump to boost the voltage supply to the memory cells, among other techniques.
Unfortunately, however, each of the above-noted techniques for improving the stability of 6T or 8T SRAM cells results in one or more disadvantages, such as, for example, increased integrated circuit (IC) area, increased power consumption, increased circuit complexity or overhead, and supply voltage penalty. Specifically, multiple fixed voltage supplies are conventionally applied to memory cells, word line drivers, and peripheral logic in an attempt to combat stability and writeability issues. However, the use of multiple voltage supplies and their conversion from on-chip is complex, and conversion efficiency is often an issue. Accordingly, conventional solutions for improving the stability of 6T and 8T SRAM cells are generally not well-suited for low-power applications. Furthermore, it is difficult to achieve a simplified solution which meets stability, performance and minimum supply voltage (Vmin) requirements of modern applications and systems.